1. Field of the Invention
The present invention generally relates to a method of forming a semiconductor device. More particularly, the present invention relates to a method for forming a carbon-containing silicon nitride layer.
2. Description of Related Art
The metal-oxide-semiconductor (MOS) field effect transistor is the most important device applied for ultra-large-integrated-circuits, such as microprocessors and semiconductor memories. The MOSFET transistor generally includes a conductive gate structure and a source/drain region disposed on both sides of the gate structure. To increase the number of components per IC chip, the device dimensions must be scaled down. As the device dimension shrinks, the channels become shorter, thus inducing undesirable short channel effects. In the prior art, the source/drain region is coupled with a lightly doped drain (LDD) structure for preventing short channel effect and hot carrier effects.
During the fabrication of the MOSFET, after forming the gate electrode, the offset spacer and/or the spacer, made of silicon oxide or silicon nitride, will be formed on the two sidewalls of the gate electrode in the subsequent processes. Afterwards, ion implantation will be performed to form the LDD structure or the source and drain regions at the two sides of the gate electrode, through the offset spacer or the spacer. For example, a composite silicon oxide/silicon nitride spacer may be formed on the sidewalls of the gate by forming an offset oxide layer and a silicon nitride layer covering the substrate and the gate electrode in sequence and then performing etching to remove a portion of the silicon nitride layer until the offset oxide layer is exposed. During the ion implantation process, the uniformity of the oxide or nitride layer of the offset spacer or the spacer has great impact on the dopant profile or junction profile of the formed LDD structure or even the source/drain region.
However, when the size of the device and the line-width shrink, the thickness of each layer and the process margin in each layer also become smaller. Especially if the offset spacer or spacer is made from a non-uniform silicon nitride layer, not only the junction depth of the subsequent doped regions region may be diverse, the effective channel length of the gate electrode may also be changed, which significantly affects the reliability and uniformity of the semiconductor devices on the wafer.